1. Field of the Invention
The present invention relates to a method for forming floating gates and, more particularly, to a method for forming self-aligned floating gates.
2. Description of the Related Art
A non-volatile memory cell is a device that retains information stored in the memory cell when the power to the cell is removed. One type of commonly used non-volatile memory cell is an electrically erasable programmable read-only-memory (EEPROM) cell. For most applications, a large number of EEPROM cells are arranged in rows and columns to form an array of EEPROM cells.
FIG. 1A shows a plan view that illustrates a portion of a prior-art EEPROM array 100. FIG. 1B shows a cross-sectional view taken along line 1Bxe2x80x941B of FIG. 1A, while FIG. 1C shows a cross-sectional view taken along line 1Cxe2x80x941C of FIG. 1A. As shown in FIGS. 1A-1C, array 100 includes a number of EEPROM cells 110 that are each formed in a p-type semiconductor material 112.
Each EEPROM cell 110 includes a n+source region 114, a n+buried region 116, and a n+drain region 118 that are formed in semiconductor material 112. In addition, a memory-transistor channel region 120 is defined between source region 114 and buried region 116, while an access-transistor channel region 122 is defined between buried region 116 and drain region 118.
Further, each EEPROM cell 110 includes a layer of tunnel oxide 124 that is formed on buried region 116, and a layer of gate oxide 128 which is formed on buried region 116 around tunnel oxide region 124. In addition, gate oxide layer 128 is formed on memory-transistor channel region 120, and access-transistor channel region 122.
Each EEPROM cell 110 also includes a memory-transistor floating gate 130 that is formed on tunnel oxide layer 124 and gate oxide layer 128 over channel region 120. Each cell 110 additionally includes an access-transistor floating gate 132 that is formed on tunnel oxide layer 126 and gate oxide layer 128 over channel region 122.
Further, each cell 110 includes a layer of interpoly dielectric 134, such as oxide-nitride-oxide (ONO), that is formed on floating gates 130 and 132. In addition, a memory-transistor control gate 136 is formed on dielectric layer 134 over floating gate 130, and an access-transistor control gate 138 is formed on dielectric layer 134 over floating gate 132.
As further shown in FIGS. 1A-1C, array 100 also includes a number of diffused source lines 140 that are formed in semiconductor material 112 so that each source region 114 in a row of source regions is connected to a diffused source line 140. Array 100 further includes a number of bit line contact regions 142 that are formed in semiconductor material 112 so that each drain region 118 is connected to a bit line contact region 142.
Array 100 additionally includes a number of word lines 144 which are formed so that each memory-transistor control gate 136 in a row of memory-transistor control gates 136 is connected to a word line 144. Further, a number of access lines 146 are formed so that each access-transistor control gate 138 in a row of access-transistor control gates 138 is connected to an access line 146. Array 100 also includes a number of field oxide regions FOX that are formed in semiconductor material 116. The field oxide regions FOX provide isolation between adjacent cells 110 in the same row of cells.
With the continuing miniaturization of integrated circuits, there is a continuing need to reduce the size of the memory array or, alternately, increase the density of the memory array. One feature that limits the size and density of array 100 is the pitch of the floating gates. Pitch is defined as the distance from a point on a floating gate to an equivalent point on an adjacent floating gate in the same row, and is shown as distance P on FIG. 1A.
The pitch has two significant components: the length of the floating gate, and the isolation spacing between adjacent floating gates in the same row of floating gates. Unless the floating gates have large xe2x80x9cwingsxe2x80x9d, a value must be added to the minimum length of the floating gates to accommodate for misalignment error. (Misalignment occurs when the floating gate is not completely formed over the channel.)
Thus, if the misalignment error can be reduced, the length of the floating gate can be reduced. This allows the pitch P to be reduced which, in turn, allows the size of the array to be reduced or the density of the array to be increased. As a result, there is a need for a technique that reduces the misalignment error and, therefore, reduces the size of the array.
The method of the present invention substantially eliminates the misalignment error added to the minimum length of floating gates by forming self-aligned floating gates. As a result, the density of a memory array can be increased.
In accordance with the present invention, the method includes the step of forming a number of trenches in a semiconductor material of a first conductivity type. The method also includes the step of forming a layer of isolation material in the trenches to fill up the trenches. Next, the layer of isolation material is planarized to form a number of isolation regions with substantially planar top surfaces. The top surface of each isolation region lies above the top surface of the semiconductor material.
The method of the present invention further includes the step of forming a first layer of dielectric material on the semiconductor material after the number of isolation regions have been formed. Next, a first layer of conductive material is formed over the first layer of dielectric material and the isolation regions. Following this, the first layer of conductive material is planarized until the layer of first conductive material is removed from the top surfaces of the isolation regions.
The present invention also includes an array of memory cells that are formed in a semiconductor material of a first conductivity type. The array has a number of spaced-apart isolation regions which each have substantially planar top surfaces that lie above the top surface of the semiconductor material.
The array also has a first layer of dielectric material that is formed on the top surface of the semiconductor material, and a number of floating gates that are formed on the first layer of dielectric material. The floating gates contact the isolation region and have top surfaces that are substantially level with the top surfaces of the isolation regions.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.